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This text is the primary in a sequence describing the extra ‘delicate’ facets of the I2C Protocol, initially developed by Philips.
Because you’re studying this sequence, I am assuming you already know what the I2C bus is, and also you’re seeking to keep away from some ache when you might want to use it in a mission. If that’s the case, you have come to the appropriate place. If not, I will be including some introductory I2C data quickly at my website.
Simply so we’re clear, this sequence is not going to embrace protection of the Excessive-speed mode, as that is considerably totally different from the design and conduct of the conventional 2-wire shared-bus implementation, and can be not that generally used. There’s loads of wonderful reference materials accessible on the Internet that covers this mode.
This is a fast listing of what’s going to be lined in the remainder of the sequence:
- lacking START
- lacking STOP
- Repeated START
- lacking information bits
- lacking ACK/NAK
- information after NAK
- back-to-back errors
- pullup resistors
- bus repeaters
- implementation utilizing a full-hardware TWI or I2C peripheral
- implementation utilizing a USI peripheral
- implementation utilizing a USART peripheral
- SMBus variations from I2C
Now, on to the good things!
For this text, we are going to deal with the three sorts of implementations you may discover in designs in the present day: full {hardware}, {hardware}/software program combine, and full software program (or ‘bit-bang’ as it’s generally referred to as).
Many microcontrollers in the present day, even some low-end gadgets, embrace a fully-hardware I2C peripheral. Atmel refers to theirs as TWI, Microchip calls theirs I2C; different distributors use comparable naming. When utilizing a fully-hardware strategy, it’s really tough to generate any sort of bus error until you misunderstand how the peripheral works or what an accurate I2C bus sequence ought to appear like. Usually, although, this strategy requires the least in-depth understanding of the protocol itself.
The USI peripheral present in some Atmel gadgets is a minimal-hardware design that is determined by software program interplay to make it an entire implementation. This versatile peripheral can really be used for I2C, SPI and UART configurations, and is suitable for low-end gadgets the place including all three peripherals could be cost-prohibitive. Though it requires extra coding than a TWI or full-hardware I2C peripheral, it’s in some methods extra versatile. This strategy requres a extra in-depth understanding of the protocol, as you might be liable for shifting from one state to the following, and it’s potential to go within the improper course.
Lastly, implementing a 100% software program strategy calls for a full understanding of the I2C protocol. Nearly each microcontroller vendor gives utility notes and code examples for creating an I2C Grasp machine utilizing a pure-software answer. In contrast to a UART, I2C is a clocked (relatively than timed) protocol, so interruptions within the execution of the protocol are tolerated properly, permitting interrupts to be serviced with out concern for shedding information. The utmost velocity of the software-based answer is finally decided by the CPU clock velocity, and normally a Grasp implementation can simply attain the 400KHz charge.
A software-based implementation of a Slave machine is way more difficult. With out {hardware} help, the software program should monitor each the SDA and the SCL traces concurrently with a purpose to detect clock edges and know positively the state of the SDA line previous to the rise or fall of SCL. Detection of a START or STOP situation will normally require using interrupts, in any other case the software program would should be 100% consumed with monitoring SCL and SDA. Software program-based Slave implementations are usually CPU-bound, requiring a number of MIPS to attain even 100KHz operation. Subsequently, true software-only Slave implementations could not even exist for some microcontroller households, and others is probably not able to reaching full 100KHz bus velocity.
With this {hardware} and software program basis having been laid, we are going to dive deeper into the protocol itself in our subsequent article. Thanks for studying!
(Copyright 2010 Robert G. Fries)
